diff options
author | Nico Huber <nico.h@gmx.de> | 2018-10-04 23:42:42 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2018-10-08 16:57:27 +0000 |
commit | d44221f9c8f3686e040ff9481829315068b321a3 (patch) | |
tree | 76337bf1cae88feda44e3c63dd7e32e964e8767d /src/include | |
parent | 834543c0c71544b547194b093b8e1da990722762 (diff) |
Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r-- | src/include/compiler.h | 32 | ||||
-rw-r--r-- | src/include/console/console.h | 1 | ||||
-rw-r--r-- | src/include/console/spi.h | 1 | ||||
-rw-r--r-- | src/include/cpu/amd/mtrr.h | 1 | ||||
-rw-r--r-- | src/include/cpu/x86/cache.h | 1 | ||||
-rw-r--r-- | src/include/cpu/x86/cr.h | 1 | ||||
-rw-r--r-- | src/include/cpu/x86/lapic.h | 1 | ||||
-rw-r--r-- | src/include/cpu/x86/msr.h | 2 | ||||
-rw-r--r-- | src/include/cpu/x86/smm.h | 1 | ||||
-rw-r--r-- | src/include/device/pci_ops.h | 1 | ||||
-rw-r--r-- | src/include/elog.h | 2 | ||||
-rw-r--r-- | src/include/halt.h | 1 | ||||
-rw-r--r-- | src/include/memory_info.h | 1 | ||||
-rw-r--r-- | src/include/reset.h | 2 | ||||
-rw-r--r-- | src/include/sar.h | 1 | ||||
-rw-r--r-- | src/include/smbios.h | 1 | ||||
-rw-r--r-- | src/include/vbe.h | 1 |
17 files changed, 0 insertions, 51 deletions
diff --git a/src/include/compiler.h b/src/include/compiler.h deleted file mode 100644 index 96c2045e4d..0000000000 --- a/src/include/compiler.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __COMPILER_H__ -#define __COMPILER_H__ - -#if defined(__WIN32) || defined(__WIN64) -#define __packed __attribute__((gcc_struct, packed)) -#else -#define __packed __attribute__((packed)) -#endif - -#define __aligned(x) __attribute__((aligned(x))) -#define __always_unused __attribute__((unused)) -#define __must_check __attribute__((warn_unused_result)) -#define __weak __attribute__((weak)) -#define __noreturn __attribute__((noreturn)) -#define __always_inline inline __attribute__((always_inline)) - -#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index ff20782398..a5f7305350 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -19,7 +19,6 @@ #include <stdint.h> #include <rules.h> #include <arch/cpu.h> -#include <compiler.h> #include <console/post_codes.h> #include <commonlib/loglevel.h> diff --git a/src/include/console/spi.h b/src/include/console/spi.h index 42566eb768..64379f8254 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -18,7 +18,6 @@ #include <rules.h> #include <stdint.h> -#include <compiler.h> void spiconsole_init(void); void spiconsole_tx_byte(unsigned char c); diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 9661b636cc..33b5939e2f 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,6 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) -#include <compiler.h> #include <cpu/x86/msr.h> void amd_setup_mtrrs(void); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 81d2ae7223..c8d26abad4 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -16,7 +16,6 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE -#include <compiler.h> #include <cpu/x86/cr.h> #define CR0_CacheDisable (CR0_CD) diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 229a67d422..5d8dcd2ad4 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -18,7 +18,6 @@ #if !defined(__ASSEMBLER__) -#include <compiler.h> #include <stdint.h> #include <arch/cpu.h> diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 5ac3c5e2e8..be6708fbbc 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -1,7 +1,6 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H -#include <compiler.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <halt.h> diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 290c54a499..85e2131e43 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -1,8 +1,6 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H -#include <compiler.h> - /* Intel SDM: Table 2-1 * IA-32 architectural MSR: Extended Feature Enable Register */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9942772f0e..3cda35b557 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -22,7 +22,6 @@ #include <arch/cpu.h> #include <types.h> -#include <compiler.h> #define SMM_DEFAULT_BASE 0x30000 #define SMM_DEFAULT_SIZE 0x10000 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9e9baa0d60..5e60e8de2d 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,7 +1,6 @@ #ifndef PCI_OPS_H #define PCI_OPS_H -#include <compiler.h> #include <stdint.h> #include <device/device.h> #include <arch/pci_ops.h> diff --git a/src/include/elog.h b/src/include/elog.h index b64953c48b..8aecf2c29b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -16,8 +16,6 @@ #ifndef ELOG_H_ #define ELOG_H_ -#include <compiler.h> - /* SMI command code for GSMI event logging */ #define ELOG_GSMI_APM_CNT 0xEF diff --git a/src/include/halt.h b/src/include/halt.h index e8f1b51976..117c6c087a 100644 --- a/src/include/halt.h +++ b/src/include/halt.h @@ -20,7 +20,6 @@ #ifdef __ROMCC__ #include <lib/halt.c> #else -#include <compiler.h> /** * halt the system reliably */ diff --git a/src/include/memory_info.h b/src/include/memory_info.h index c9554b8a4b..1b30702c33 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -17,7 +17,6 @@ #define _MEMORY_INFO_H_ #include <stdint.h> -#include <compiler.h> #define DIMM_INFO_SERIAL_SIZE 4 #define DIMM_INFO_PART_NUMBER_SIZE 21 diff --git a/src/include/reset.h b/src/include/reset.h index 48999164bb..cf9d5744b2 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -1,8 +1,6 @@ #ifndef RESET_H #define RESET_H -#include <compiler.h> - /* Generic reset functions. Call from code that wants to trigger a reset. */ /* Super-hard reset specific to some Intel SoCs. */ diff --git a/src/include/sar.h b/src/include/sar.h index e1e0fcb2d7..9da4dd943c 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -15,7 +15,6 @@ #ifndef _SAR_H_ #define _SAR_H_ -#include <compiler.h> #include <stdint.h> #define NUM_SAR_LIMITS 4 diff --git a/src/include/smbios.h b/src/include/smbios.h index 631a1a59be..574b92469f 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,7 +19,6 @@ #define SMBIOS_H #include <types.h> -#include <compiler.h> unsigned long smbios_write_tables(unsigned long start); int smbios_add_string(u8 *start, const char *str); diff --git a/src/include/vbe.h b/src/include/vbe.h index ceceff29fb..2c40d0507e 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -13,7 +13,6 @@ #ifndef VBE_H #define VBE_H -#include <compiler.h> #include <boot/coreboot_tables.h> // these structs are for input from and output to OF typedef struct { |