diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-11-20 19:32:51 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-23 03:47:18 +0000 |
| commit | c87ab01c2d2e70c64d88d3afd4d49a0687b05b3c (patch) | |
| tree | acb2ec7d48f9600b787b0a1cdd528a5e5e20e630 /src/include | |
| parent | 4911942e949f40d0da0ed7debeadef1f3eccf17c (diff) | |
cpu/intel/car: Define post codes
This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.
The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values. Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.
The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.
POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/intel/post_codes.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h new file mode 100644 index 0000000000..3db0aeb939 --- /dev/null +++ b/src/include/cpu/intel/post_codes.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CPU_INTEL_CAR_POST_CODES_H +#define CPU_INTEL_CAR_POST_CODES_H + +#define POST_BOOTBLOCK_CAR 0x20 +#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POST_SOC_BSP_INIT 0x23 +#define POST_SOC_COUNT_CORES 0x24 +#define POST_SOC_CPU_HYPER_THREADING 0x25 +#define POST_SOC_CPU_SIBLING_DELAY 0x26 +#define POST_SOC_CPU_AP_INIT 0x27 +#define POST_SOC_SET_MTRR_BASE 0x28 +#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POST_SOC_AP_HALT 0x29 +#define POST_SOC_SET_CAR_BASE 0x2a +#define POST_SOC_ENABLE_MTRRS 0x2b +#define POST_SOC_ENABLE_CACHE 0x2c +#define POST_SOC_DISABLE_CACHE 0x2d +#define POST_SOC_FILL_CACHE 0x2e +#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f + +#define POST_POSTCAR_DISABLE_CACHE 0x30 +#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POST_POSTCAR_TEARDOWN_DONE 0x32 + +#endif |