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| author | Werner Zeh <werner.zeh@siemens.com> | 2023-02-27 08:50:15 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-28 06:04:53 +0000 |
| commit | b40b2b1933934d93f88542518415458583c80e47 (patch) | |
| tree | f63dcd709a2a86f7b841f705e861bf80e16c4f30 /src/include | |
| parent | 63c1f7b18767c444a876b224785543ac58482a56 (diff) | |
include/device/pci_def.h: Fix typo in comment
Fix typo in the comment for Common Clock Configuration.
Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_def.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index c13e054616..69ff79d91a 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -431,7 +431,7 @@ #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ -#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock Configuration */ #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ #define PCI_EXP_LNKSTA 18 /* Link Status */ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ |