diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-31 14:43:57 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-01-09 04:30:39 +0000 |
| commit | ad87a82ca7d960ee696dd57c013d75609212eb66 (patch) | |
| tree | c1eb27873647b8818e95c3273af712eee474d9a3 /src/include | |
| parent | 93f12985e6b75f8a7b576a5a6b795ca3a8823395 (diff) | |
security/intel/txt: Add helper function to disable TXT
Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP
firmware can disable TXT if TXT fails or TPM is already enabled.
On platforms with TXT disabled, the memory can be unlocked using
MSR 0x2e6.
TEST=Able to perform disable_txt on SoC SKUs with TXT enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 33eb457f1a..d369972908 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,6 +81,7 @@ #define MCA_STATUS_LO_ERRCODE_EXT_SH 16 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) +#define IA32_LT_UNLOCK_MEMORY 0x2e6 #define IA32_MC0_ADDR 0x402 #define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank)) #define IA32_MC0_MISC 0x403 |