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authorSowmya V <v.sowmya@intel.com>2024-04-22 19:20:03 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-04-23 21:09:52 +0000
commit859df7160a5982eeaff1aa18ce40fbd2ae6ee107 (patch)
treec14012398d6a34a8c40b72045fc410ee094d50b3 /src/include
parent282b48e2f0e5352fcbccae2a3e5b911e119265ee (diff)
soc/intel/alderlake: Add Twinlake graphics device IDs
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 7831d5b575..d3ba149afb 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4147,6 +4147,8 @@
#define PCI_DID_INTEL_RPL_U_GT4 0xa7ac
#define PCI_DID_INTEL_RPL_U_GT5 0xa7ad
#define PCI_DID_INTEL_LNL_M_GT2 0x64a0
+#define PCI_DID_INTEL_TWL_GT1_1 0x46D3
+#define PCI_DID_INTEL_TWL_GT1_2 0x46D4
/* Intel Northbridge Ids */
#define PCI_DID_INTEL_APL_NB 0x5af0