diff options
| author | Jonathon Hall <jonathon.hall@puri.sm> | 2023-05-01 13:42:46 -0400 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2023-05-08 17:51:08 +0000 |
| commit | 78f8343c70551bdb8f2cc3716aed9f339a85530b (patch) | |
| tree | f99255176b959296f071e4db04585d6dbc713dae /src/include | |
| parent | e12b313844da92ff91dd0ff47a85c2fd0789a475 (diff) | |
drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses
Configure the CMOS bank I/O base addresses with
PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The
defaults remain the same.
Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74903
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 383c41fc66..78184214a3 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -6,9 +6,10 @@ #include <arch/io.h> #include <types.h> -#define RTC_BASE_PORT 0x70 +#define RTC_BASE_PORT_BANK0 (CONFIG_PC_CMOS_BASE_PORT_BANK0) +#define RTC_BASE_PORT_BANK1 (CONFIG_PC_CMOS_BASE_PORT_BANK1) -#define RTC_PORT(x) (RTC_BASE_PORT + (x)) +#define RTC_PORT_BANK0(x) (RTC_BASE_PORT_BANK0 + (x)) /* control registers - Moto names */ @@ -107,24 +108,24 @@ static inline unsigned char cmos_read(unsigned char addr) { - int offs = 0; + int port = RTC_BASE_PORT_BANK0; if (addr >= 128) { - offs = 2; + port = RTC_BASE_PORT_BANK1; addr -= 128; } - outb(addr, RTC_BASE_PORT + offs + 0); - return inb(RTC_BASE_PORT + offs + 1); + outb(addr, port + 0); + return inb(port + 1); } static inline void cmos_write_inner(unsigned char val, unsigned char addr) { - int offs = 0; + int port = RTC_BASE_PORT_BANK0; if (addr >= 128) { - offs = 2; + port = RTC_BASE_PORT_BANK1; addr -= 128; } - outb(addr, RTC_BASE_PORT + offs + 0); - outb(val, RTC_BASE_PORT + offs + 1); + outb(addr, port + 0); + outb(val, port + 1); } static inline u8 cmos_disable_rtc(void) |