diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-12-28 11:43:49 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-01-04 07:22:58 +0000 |
| commit | 5a04746714ddf1fdf4c0e1c9ed8cea4aa7fea511 (patch) | |
| tree | 7aa46ab7cc54288442bfa0f1667e49a1f425e59f /src/include | |
| parent | 046100590870042db986e622d5126b9daefc596e (diff) | |
spd.h: Move enum ddr2_module_type to ddr2.h
Move specific enum ddr2_module_type to <device/dram/ddr2.h>.
Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/dram/ddr2.h | 13 | ||||
| -rw-r--r-- | src/include/spd.h | 12 |
2 files changed, 5 insertions, 20 deletions
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 6200fdedd6..9277ffbc02 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -18,15 +18,12 @@ #include <spd.h> #include <device/dram/common.h> -/* - * Module type (byte 20, bits 5:0) of SPD - * This definition is specific to DDR2. DDR3 SPDs have a different structure. - */ +/* Byte 20 [5:0]: DDR2 Module type information */ enum spd_dimm_type_ddr2 { - SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, - SPD_DDR2_DIMM_TYPE_RDIMM = 0x01, - SPD_DDR2_DIMM_TYPE_UDIMM = 0x02, - SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DDR2_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DDR2_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR2_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR2_DIMM_TYPE_SO_DIMM = 0x04, SPD_DDR2_DIMM_TYPE_72B_SO_CDIMM = 0x06, SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM = 0x07, SPD_DDR2_DIMM_TYPE_MICRO_DIMM = 0x08, diff --git a/src/include/spd.h b/src/include/spd.h index 7a6e5ab7e0..25d04639fc 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,18 +201,6 @@ enum spd_memory_type { #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 20 [5:0]: DDR2 Module type information */ -enum ddr2_module_type { - DDR2_SPD_RDIMM = 0x01, - DDR2_SPD_UDIMM = 0x02, - DDR2_SPD_SODIMM = 0x04, - DDR2_SPD_72B_SO_CDIMM = 0x06, - DDR2_SPD_72B_SO_RDIMM = 0x07, - DDR2_SPD_MICRO_DIMM = 0x08, - DDR2_SPD_MINI_RDIMM = 0x10, - DDR2_SPD_MINI_UDIMM = 0x20, -}; - /* Byte 3 [3:0]: DDR3 Module type information */ enum ddr3_module_type { DDR3_SPD_RDIMM = 0x01, |