diff options
| author | Tim Crawford <tcrawford@system76.com> | 2023-07-07 09:59:56 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-14 14:31:24 +0000 |
| commit | 53c6eea2d42fb4b5f3a6d31bc4bdf538767e815b (patch) | |
| tree | 34dbd201e87b760a89514e02e63d50bcc1c5bf08 /src/include | |
| parent | 0bde1829e767f4cc9c0789514d1e243c53f94075 (diff) | |
soc/intel/adl: Add Raptor Lake-HX definitions
Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13)
to edk2 payload and then OS.
Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.8)
Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b311991683..5893509b35 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4048,6 +4048,10 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_RPL_HX_GT1 0xa788 +#define PCI_DID_INTEL_RPL_HX_GT2 0xa78b +#define PCI_DID_INTEL_RPL_HX_GT3 0x4688 +#define PCI_DID_INTEL_RPL_HX_GT4 0x468b #define PCI_DID_INTEL_RPL_S_GT0 0xa79f #define PCI_DID_INTEL_RPL_S_GT1_1 0xa780 #define PCI_DID_INTEL_RPL_S_GT1_2 0xa782 @@ -4177,6 +4181,14 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 +#define PCI_DID_INTEL_RPL_HX_ID_1 0xa702 +#define PCI_DID_INTEL_RPL_HX_ID_2 0xa729 +#define PCI_DID_INTEL_RPL_HX_ID_3 0xa728 +#define PCI_DID_INTEL_RPL_HX_ID_4 0xa72a +#define PCI_DID_INTEL_RPL_HX_ID_5 0xa719 +#define PCI_DID_INTEL_RPL_HX_ID_6 0x4637 +#define PCI_DID_INTEL_RPL_HX_ID_7 0x463b +#define PCI_DID_INTEL_RPL_HX_ID_8 0x4647 #define PCI_DID_INTEL_RPL_S_ID_1 0xa700 #define PCI_DID_INTEL_RPL_S_ID_2 0xa701 #define PCI_DID_INTEL_RPL_S_ID_3 0xa703 |