cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

6 files changed, 53 insertions, 129 deletions

diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h
deleted file mode 100644
index 3838ce1b84..0000000000
--- a/src/include/cpu/amd/amdfam12.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef CPU_AMD_FAM12_H
-#define CPU_AMD_FAM12_H
-
-#define HWCR_MSR			0xC0010015
-#define NB_CFG_MSR			0xC001001f
-#define LS_CFG_MSR			0xC0011020
-#define IC_CFG_MSR			0xC0011021
-#define DC_CFG_MSR			0xC0011022
-#define BU_CFG_MSR			0xC0011023
-#define BU_CFG2_MSR			0xC001102A
-
-#define CPU_ID_FEATURES_MSR		0xC0011004
-#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
-
-#endif /* CPU_AMD_FAM12_H */
diff --git a/src/include/cpu/amd/amdfam14.h b/src/include/cpu/amd/amdfam14.h
deleted file mode 100644
index ec5d34b9e9..0000000000
--- a/src/include/cpu/amd/amdfam14.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef CPU_AMD_FAM14_H
-#define CPU_AMD_FAM14_H
-
-#define HWCR_MSR			0xC0010015
-#define NB_CFG_MSR			0xC001001f
-#define LS_CFG_MSR			0xC0011020
-#define IC_CFG_MSR			0xC0011021
-#define DC_CFG_MSR			0xC0011022
-#define BU_CFG_MSR			0xC0011023
-#define BU_CFG2_MSR			0xC001102A
-
-#define CPU_ID_FEATURES_MSR		0xC0011004
-#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
-
-#endif /* CPU_AMD_FAM14_H */
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
index 271af8aef5..18feaffa45 100644
--- a/src/include/cpu/amd/amdfam15.h
+++ b/src/include/cpu/amd/amdfam15.h
@@ -19,9 +19,6 @@
 #include <types.h>
 #include <cpu/x86/msr.h>
 
-#define MCG_CAP				0x00000179
-# define MCA_BANKS_MASK			0xff
-#define MC0_CTL				0x00000400
 #define MC0_STATUS			0x00000401
 # define MCA_STATUS_HI_VAL		BIT(63 - 32)
 # define MCA_STATUS_HI_OVERFLOW		BIT(62 - 32)
@@ -189,30 +186,4 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
 	return MCA_ERRTYPE_UNKNOWN;
 }
 
-#define MSR_SMM_BASE			0xC0010111
-#define MSR_TSEG_BASE			0xC0010112
-#define MSR_SMM_MASK			0xC0010113
-# define SMM_TSEG_VALID			(1 << 1)
-# define SMM_TSEG_WB			(6 << 12)
-#define HWCR_MSR			0xC0010015
-# define SMM_LOCK			(1 << 0)
-#define NB_CFG_MSR			0xC001001f
-
-#define MMIO_CONF_BASE			0xC0010058
-# define MMIO_BUS_RANGE_SHIFT		2
-# define MMIO_RANGE_EN			(1 << 0)
-
-#define PSTATE_0_MSR			0xC0010064
-
-#define LS_CFG_MSR			0xC0011020
-#define IC_CFG_MSR			0xC0011021
-#define DC_CFG_MSR			0xC0011022
-#define CU_CFG_MSR			0xC0011023
-#define CU_CFG2_MSR			0xC001102A
-
-#define CPU_ID_FEATURES_MSR		0xC0011004
-#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
-
-#define CORE_PERF_BOOST_CTRL		0x15C
-
 #endif /* CPU_AMD_FAM15_H */
diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h
deleted file mode 100644
index 8b7503d906..0000000000
--- a/src/include/cpu/amd/amdfam16.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef CPU_AMD_FAM16_H
-#define CPU_AMD_FAM16_H
-
-#define MCG_CAP				0x00000179
-# define MCA_BANKS_MASK			0xff
-#define MC0_STATUS			0x00000401
-#define HWCR_MSR			0xC0010015
-#define NB_CFG_MSR			0xC001001f
-
-#define LS_CFG_MSR			0xC0011020
-#define IC_CFG_MSR			0xC0011021
-#define DC_CFG_MSR			0xC0011022
-#define CU_CFG_MSR			0xC0011023
-#define CU_CFG2_MSR			0xC001102A
-
-#define CPU_ID_FEATURES_MSR		0xC0011004
-#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
-
-#endif /* CPU_AMD_FAM16_H */
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 614c576d03..46ec70d3c9 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -15,17 +15,65 @@
  * GNU General Public License for more details.
  */
 
+/* This file applies to AMD64 products.
+ * The definitions come from the AMD64 Programmers Manual vol2
+ * Revision 3.30 and/or the device's BKDG.
+ */
+
 #ifndef CPU_AMD_MSR_H
 #define CPU_AMD_MSR_H
 
 #include <cpu/x86/msr.h>
 
+#define CPUID_EXT_PM			0x80000007
+#define CPUID_MODEL			1
+#define MC4_MISC0			0x00000413
+#define MC4_MISC1			0xC0000408
+#define MC4_MISC2			0xC0000409
+#define FS_Base				0xC0000100
+#define HWCR_MSR                        0xC0010015
+#define NB_CFG_MSR                      0xC001001f
+#define FidVidStatus			0xC0010042
+#define MC1_CTL_MASK			0xC0010045
+#define MC4_CTL_MASK			0xC0010048
+#define MSR_INTPEND			0xC0010055
+#define MMIO_CONF_BASE			0xC0010058
+#define  MMIO_RANGE_EN			(1 << 0)
+#define  MMIO_BUS_RANGE_SHIFT		(1 << 1)
+	/* P-state Current Limit Register */
+#define PS_LIM_REG			0xC0010061
+	 /* P-state Maximum Value shift position */
+#define  PS_MAX_VAL_SHFT		4
+	/* P-state Control Register */
+#define PS_CTL_REG			0xC0010062
+	 /* P-state Control Register CMD Mask OFF */
+#define  PS_CMD_MASK_OFF		~(7)
+	 /* P-state Status Mask */
+#define  PS_STS_MASK			7
+	/* P-state Status Register */
+#define PS_STS_REG			0xC0010063
+#define PSTATE_0_MSR			0xC0010064
+#define PSTATE_1_MSR			0xC0010065
+#define PSTATE_2_MSR			0xC0010066
+#define PSTATE_3_MSR			0xC0010067
+#define PSTATE_4_MSR			0xC0010068
+
+#define MSR_COFVID_STS			0xC0010071
+#define MSR_CSTATE_ADDRESS		0xC0010073
+#define OSVW_ID_Length			0xC0010140
+#define OSVW_Status			0xC0010141
+
 #define SMM_BASE_MSR			0xC0010111
 #define SMM_ADDR_MSR			0xC0010112
 #define SMM_MASK_MSR			0xC0010113
+#define  SMM_LOCK			(1 << 0)
+#define  SMM_TSEG_VALID			(1 << 1)
+#define  SMM_TSEG_WB			(6 << 12)
 
-#define HWCR_MSR			0xC0010015
-#define NB_CFG_MSR			0xC001001f
+#define CPU_ID_FEATURES_MSR		0xC0011004
+#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
+#define CPU_ID_HYPER_EXT_FEATURES	0xC001100d
+#define LOGICAL_CPUS_NUM_MSR		0xC001100d
 #define LS_CFG_MSR			0xC0011020
 #define IC_CFG_MSR			0xC0011021
 #define DC_CFG_MSR			0xC0011022
@@ -38,9 +86,6 @@
 #define LS_CFG2_MSR			0xC001102D
 #define IBS_OP_DATA3_MSR		0xC0011037
 
-#define CPU_ID_FEATURES_MSR		0xC0011004
-#define CPU_ID_HYPER_EXT_FEATURES	0xC001100d
-#define LOGICAL_CPUS_NUM_MSR		0xC001100d
-#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
+#define CORE_PERF_BOOST_CTRL		0x15c
 
 #endif /* CPU_AMD_MSR_H */
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 62e56b7a28..032ce4ecb6 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -25,6 +25,8 @@
 #define IA32_MPERF			0xe7
 #define IA32_APERF			0xe8
 #define IA32_MCG_CAP			0x179
+#define  MCG_CTL_P			(1 << 3)
+#define  MCA_BANKS_MASK			0xff
 #define IA32_PERF_STATUS		0x198
 #define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b