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authorShuo Liu <shuo.liu@intel.com>2024-03-29 00:42:28 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-04-18 11:38:02 +0000
commit271ee0745e4bc104949b20f433216f1f0a06fb46 (patch)
treef47c2c5233f548210836656fc26ea77334b2bdae /src/include
parente56a41b33fd2e52a6bfeec5a0a845c9c2d4e9b01 (diff)
device/device_util: Rename dev_get_pci_domain
In coreboot, domain indicates hardware units that provide/group resource windows, For Xeon-SP, domains are PCIe compatible and further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX. Rename dev_get_pci_domain to dev_get_domain to align with coreboot concept and distinguish from Xeon-SP concept. TEST=Build and boot on intel/archercity CRB Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/device.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 7f73d2b362..ac7e86917e 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -182,7 +182,7 @@ void assign_resources(struct bus *bus);
const char *dev_name(const struct device *dev);
const char *dev_path(const struct device *dev);
u32 dev_path_encode(const struct device *dev);
-const struct device *dev_get_pci_domain(const struct device *dev);
+const struct device *dev_get_domain(const struct device *dev);
void dev_set_enabled(struct device *dev, int enable);
void disable_children(struct bus *bus);
bool dev_is_active_bridge(struct device *dev);