diff options
| author | Jeremy Soller <jackpot51@gmail.com> | 2023-05-17 14:52:03 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-23 20:21:39 +0000 |
| commit | 14d69d03b79958ca35ed39405570ff37cfebfe1f (patch) | |
| tree | 57c846ac65a2183aa43fbba80460fa0cdd5c1014 /src/include | |
| parent | f99d6700f167b70d883dd4ecf9a82bff21fea5d5 (diff) | |
soc/intel/common: Add RPP-S PCI IDs
Add PCI IDs to support Raptor Point PCH.
Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0245086045..40df090088 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3467,6 +3467,35 @@ #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d +#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38 +#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39 +#define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a +#define PCI_DID_INTEL_RPP_S_PCIE_RP4 0x7a3b +#define PCI_DID_INTEL_RPP_S_PCIE_RP5 0x7a3c +#define PCI_DID_INTEL_RPP_S_PCIE_RP6 0x7a3d +#define PCI_DID_INTEL_RPP_S_PCIE_RP7 0x7a3e +#define PCI_DID_INTEL_RPP_S_PCIE_RP8 0x7a3f +#define PCI_DID_INTEL_RPP_S_PCIE_RP9 0x7a30 +#define PCI_DID_INTEL_RPP_S_PCIE_RP10 0x7a31 +#define PCI_DID_INTEL_RPP_S_PCIE_RP11 0x7a32 +#define PCI_DID_INTEL_RPP_S_PCIE_RP12 0x7a33 +#define PCI_DID_INTEL_RPP_S_PCIE_RP13 0x7a34 +#define PCI_DID_INTEL_RPP_S_PCIE_RP14 0x7a35 +#define PCI_DID_INTEL_RPP_S_PCIE_RP15 0x7a36 +#define PCI_DID_INTEL_RPP_S_PCIE_RP16 0x7a37 +#define PCI_DID_INTEL_RPP_S_PCIE_RP17 0x7a40 +#define PCI_DID_INTEL_RPP_S_PCIE_RP18 0x7a41 +#define PCI_DID_INTEL_RPP_S_PCIE_RP19 0x7a42 +#define PCI_DID_INTEL_RPP_S_PCIE_RP20 0x7a43 +#define PCI_DID_INTEL_RPP_S_PCIE_RP21 0x7a44 +#define PCI_DID_INTEL_RPP_S_PCIE_RP22 0x7a45 +#define PCI_DID_INTEL_RPP_S_PCIE_RP23 0x7a46 +#define PCI_DID_INTEL_RPP_S_PCIE_RP24 0x7a47 +#define PCI_DID_INTEL_RPP_S_PCIE_RP25 0x7a48 +#define PCI_DID_INTEL_RPP_S_PCIE_RP26 0x7a49 +#define PCI_DID_INTEL_RPP_S_PCIE_RP27 0x7a4a +#define PCI_DID_INTEL_RPP_S_PCIE_RP28 0x7a4b + /* Intel SATA device Ids */ #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 @@ -3553,6 +3582,7 @@ #define PCI_DID_INTEL_MTL_SATA 0x7e63 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 +#define PCI_DID_INTEL_RPP_S_SATA 0x7a62 /* Intel PMC device Ids */ #define PCI_DID_INTEL_SPT_LP_PMC 0x9d21 @@ -3688,6 +3718,13 @@ #define PCI_DID_INTEL_ADP_M_N_I2C4 0x54c5 #define PCI_DID_INTEL_ADP_M_N_I2C5 0x54c6 +#define PCI_DID_INTEL_RPP_S_I2C0 0x7a4c +#define PCI_DID_INTEL_RPP_S_I2C1 0x7a4d +#define PCI_DID_INTEL_RPP_S_I2C2 0x7a4e +#define PCI_DID_INTEL_RPP_S_I2C3 0x7a4f +#define PCI_DID_INTEL_RPP_S_I2C4 0x7a7c +#define PCI_DID_INTEL_RPP_S_I2C5 0x7a7d + #define PCI_DID_INTEL_MTL_I2C0 0x7e78 #define PCI_DID_INTEL_MTL_I2C1 0x7e79 #define PCI_DID_INTEL_MTL_I2C2 0x7e7a @@ -3765,6 +3802,11 @@ #define PCI_DID_INTEL_ADP_M_N_UART2 0x54c7 #define PCI_DID_INTEL_ADP_M_N_UART3 0x54da +#define PCI_DID_INTEL_RPP_S_UART0 0x7a28 +#define PCI_DID_INTEL_RPP_S_UART1 0x7a29 +#define PCI_DID_INTEL_RPP_S_UART2 0x7a7e +#define PCI_DID_INTEL_RPP_S_UART3 0x7a5c + #define PCI_DID_INTEL_MTL_UART0 0x7e25 #define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART2 0x7e52 @@ -3850,6 +3892,12 @@ #define PCI_DID_INTEL_ADP_M_N_SPI1 0x54ab #define PCI_DID_INTEL_ADP_M_SPI2 0x54fb +#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI 0x7a24 +#define PCI_DID_INTEL_RPP_S_SPI0 0x7a2a +#define PCI_DID_INTEL_RPP_S_SPI1 0x7a2b +#define PCI_DID_INTEL_RPP_S_SPI2 0x7a7b +#define PCI_DID_INTEL_RPP_S_SPI3 0x7a79 + #define PCI_DID_INTEL_SPR_HWSEQ_SPI 0x1bca #define PCI_DID_INTEL_MTL_HWSEQ_SPI 0x7e23 @@ -4156,6 +4204,7 @@ #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 +#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4195,6 +4244,7 @@ #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e +#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4265,6 +4315,14 @@ #define PCI_DID_INTEL_ADP_S_AUDIO_8 0x7ad7 #define PCI_DID_INTEL_ADP_P_AUDIO 0x51c8 #define PCI_DID_INTEL_RPP_P_AUDIO 0x51ca +#define PCI_DID_INTEL_RPP_S_AUDIO_1 0x7a50 +#define PCI_DID_INTEL_RPP_S_AUDIO_2 0x7a51 +#define PCI_DID_INTEL_RPP_S_AUDIO_3 0x7a52 +#define PCI_DID_INTEL_RPP_S_AUDIO_4 0x7a53 +#define PCI_DID_INTEL_RPP_S_AUDIO_5 0x7a54 +#define PCI_DID_INTEL_RPP_S_AUDIO_6 0x7a55 +#define PCI_DID_INTEL_RPP_S_AUDIO_7 0x7a56 +#define PCI_DID_INTEL_RPP_S_AUDIO_8 0x7a57 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1 0x54c8 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2 0x54c9 @@ -4322,6 +4380,10 @@ #define PCI_DID_INTEL_ADP_M_CSE1 0x54e1 #define PCI_DID_INTEL_ADP_M_CSE2 0x54e4 #define PCI_DID_INTEL_ADP_M_CSE3 0x54e5 +#define PCI_DID_INTEL_RPP_S_CSE0 0x7a68 +#define PCI_DID_INTEL_RPP_S_CSE1 0x7a69 +#define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c +#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 /* Intel XDCI device Ids */ @@ -4342,6 +4404,7 @@ #define PCI_DID_INTEL_ADP_S_XDCI 0x7ae1 #define PCI_DID_INTEL_ADP_TCSS_XDCI 0x460e #define PCI_DID_INTEL_ADP_M_XDCI 0x54ee +#define PCI_DID_INTEL_RPP_S_XDCI 0x7a61 #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 @@ -4485,6 +4548,10 @@ #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73 /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d @@ -4495,6 +4562,7 @@ #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM 0xa0ef #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d +#define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM 0x7a27 /* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 |