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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-05 07:56:38 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-04-07 02:31:36 +0000
commitd2cdfff63b6e2376fad729252a57acfd2b4418ea (patch)
tree01d0ccd1e0826c9449a6c4f1781e7feb813fe537 /src/include
parentbf0970e762a6611cef06af761bc2dec068d439bb (diff)
device/pci: Rewrite PCI MMCONF with symbol reference
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_mmio_cfg.h55
-rw-r--r--src/include/device/pci_type.h4
2 files changed, 41 insertions, 18 deletions
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h
index e7019151aa..5567ed86ae 100644
--- a/src/include/device/pci_mmio_cfg.h
+++ b/src/include/device/pci_mmio_cfg.h
@@ -20,55 +20,74 @@
#include <device/mmio.h>
#include <device/pci_type.h>
+#if !defined(__ROMCC__)
+
+/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
+ * prevent some sub-optimal constant folding. */
+extern u8 *const pci_mmconf;
+
+/* Using a unique datatype for MMIO writes makes the pointers to _not_
+ * qualify for pointer aliasing with any other objects in memory.
+ *
+ * MMIO offset is a value originally derived from 'struct device *'
+ * in ramstage. For the compiler to not discard this MMIO offset value
+ * from CPU registers after any MMIO writes, -fstrict-aliasing has to
+ * be also set for the build.
+ *
+ * Bottom 12 bits (4 KiB) are reserved to address the registers of a
+ * single PCI function. Declare the bank as a union to avoid some casting
+ * in the functions below.
+ */
+union pci_bank {
+ uint8_t reg8[4096];
+ uint16_t reg16[4096 / sizeof(uint16_t)];
+ uint32_t reg32[4096 / sizeof(uint32_t)];
+};
+
+static __always_inline
+volatile union pci_bank *pcicfg(pci_devfn_t dev)
+{
+ return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)];
+}
static __always_inline
uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
{
- void *addr;
- addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
- return read8(addr);
+ return pcicfg(dev)->reg8[reg];
}
static __always_inline
uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
{
- void *addr;
- addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
- return read16(addr);
+ return pcicfg(dev)->reg16[reg / sizeof(uint16_t)];
}
static __always_inline
uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
{
- void *addr;
- addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
- return read32(addr);
+ return pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
}
static __always_inline
void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
{
- void *addr;
- addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
- write8(addr, value);
+ pcicfg(dev)->reg8[reg] = value;
}
static __always_inline
void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
{
- void *addr;
- addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
- write16(addr, value);
+ pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value;
}
static __always_inline
void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
{
- void *addr;
- addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
- write32(addr, value);
+ pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value;
}
+#endif /* !defined(__ROMCC__) */
+
#if CONFIG(MMCONF_SUPPORT)
/* Avoid name collisions as different stages have different signature
diff --git a/src/include/device/pci_type.h b/src/include/device/pci_type.h
index 27d35589cc..4d8c2a3d08 100644
--- a/src/include/device/pci_type.h
+++ b/src/include/device/pci_type.h
@@ -18,6 +18,10 @@
typedef u32 pci_devfn_t;
+/* Convert pci_devfn_t to offset in MMCONF space.
+ * As it is one-to-one, nothing needs to be done. */
+#define PCI_DEVFN_OFFSET(x) ((x))
+
#define PCI_DEV(SEGBUS, DEV, FN) ( \
(((SEGBUS) & 0xFFF) << 20) | \
(((DEV) & 0x1F) << 15) | \