diff options
| author | V Sowmya <v.sowmya@intel.com> | 2020-12-02 22:32:07 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-05 05:36:29 +0000 |
| commit | 5fc798f40e994b57047512a9fa6ff9a13630cfa4 (patch) | |
| tree | a652b545450f5b8b7f12464b2edf0cd852976e2d /src/include | |
| parent | 0247fcf87b8574b8b9ecd1f49d5b7f4087384c83 (diff) | |
device/pci_id: Add TCSS PCI IDs for Alderlake
Add the PCI IDs for Alderlake TCSS,
* USB xHCI
* USB xDCI
* TBT DMA
* TBT PCIe
Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48242
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 51c0abf5f3..9e6ac64861 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3871,6 +3871,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded #define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 +#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI 0x461e /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3984,6 +3985,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee #define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 +#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XDCI 0x460e /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 @@ -4008,8 +4010,14 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP0 0x466e +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP1 0x463f +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP2 0x462f +#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP3 0x461f #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b #define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d +#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA0 0x463e +#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA1 0x466d /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 |