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authorSubrata Banik <subrata.banik@intel.com>2019-02-02 13:32:49 +0530
committerFurquan Shaikh <furquan@google.com>2019-03-16 22:48:06 +0000
commit41483c9dff9bd68b4c67b947c4cd7175951b9723 (patch)
treeaec170fe3513fdd2156309be0eced2ed59617e7d /src/include
parentebd8a4f90cf58cd03a95fcc01acea1c59b0cad4e (diff)
soc/intel/cannonlake: Add required FSP UPD changes for CML
This patch adds required FSP UPD changes for CometLake SoC. Also this patch tries to create common parse logic for CometLake as well as cannonlake SOC. We parse device tree parameters for PCI devices and fill values in FSP UPDs. We fill UPDs based on pci device config as well as SerialIoDev config of devicetree. For PCI devices, if PCI device is disabled from devicetree, we'll assign disable value to FSP UPD. In case devicetree doesn't fill this parameter or value is invalid in SerialIoDev config, default mode will be set to PCI. In case of valid value, we'll fill the same value into FSP UPD. BUG=none BRANCH=none TEST=check if CML board boots and proper UPD values are filled. Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
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