summaryrefslogtreecommitdiff
path: root/src/include
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2014-07-17 13:08:06 -0500
committerMarc Jones <marc.jones@se-eng.com>2015-03-13 00:02:54 +0100
commit01dde90eb9c070018fc11b007159c8d130b2809d (patch)
tree4a76a7efc98b6ad469b463091b0bbb53c9b27193 /src/include
parentb397f011497e9ea3fa06ed8d3bf29947e55a2677 (diff)
armv8: correct dcache line size calculation
The CCSIDR_EL1 register has cache attribute information for a given cache selection in CSSELR_EL1. However, the cache isn't being selected before reading CCSIDR_EL1. Instead use CTR_EL0 which better fits with the semantics of dcache_line_bytes(). CTR_EL0 has the minimum data cache line size of all caches in the system encoded in 19:16 encoded as lg(line size in words). BUG=None TEST=Built. Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208720 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0 Reviewed-on: http://review.coreboot.org/8642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions