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authorMatt DeVillier <matt.devillier@gmail.com>2024-07-09 16:47:59 -0500
committerFelix Held <felix-coreboot@felixheld.de>2024-07-11 00:13:20 +0000
commitbaec1c858d425d7acfa321f4d20f22903e018364 (patch)
treea7df013fa0dc82ec7f716fef883d1905b05082cf /src/include/wrdd.h
parentae77d8afacb37f4ee1a0ee9942d9a0249c57ed8a (diff)
soc/amd/mendocino: Fix APOB NV size/base for non-vboot builds
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Skyrim boards. TEST=build/boot Skyrim (Frostflow), verify RAM training only run on first boot after flashing. Change-Id: I9be1699d675331b46ee9c42570700c2b72588025 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/include/wrdd.h')
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