diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-07-12 17:32:52 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 21:58:37 +0200 |
commit | b72c67b713c7a651416be28831d80a77ef1ce617 (patch) | |
tree | 05c842f4a23ec773076ca0a2f4a48faf9ca136eb /src/include/wrdd.h | |
parent | 1318e88352d7b20661adec82769f46308471d739 (diff) |
soc/intel/apollolake: set gpio interrupt polarity in ITSS
For APIC routed gpios, set the corresponding interrupt polarity
for the associated IRQ based on the gpio pad's invert setting.
This allows for the APIC redirection entries to match the hardware
active polarity once the double inversion takes place to meet
apollolake interrupt triggering constraints.
BUG=chrome-os-partner:54955
Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15648
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include/wrdd.h')
0 files changed, 0 insertions, 0 deletions