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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-07-24 11:11:03 +0530
committerDuncan Laurie <dlaurie@chromium.org>2017-07-24 23:59:51 +0000
commit130f266c6e19d5078313fb5f6e29c0a198dbc734 (patch)
tree346062da5a4383e6e716e733a6f750e5977a11e8 /src/include/timer.h
parent695576799bcaa0967bb1af30f65fd38b3532b8bd (diff)
soc/intel/common/block: Add max SPI transaction time-out as 5 sec
Earlier 15ms time-out was kept for SPI transactions which was not enough for SPI Erase transactions. Increase the max time-out time to 5 secs which was present in SKL before common code. This increase in time-out won't disturb other SPI transactions like Read, Write or Read Status, since, for those it will come out of the loop once FDONE bit or FCERR bit is set. BUG=b:63959637 BRANCH=none TEST=Built and booted poppy and all SPI transactions succeeded. Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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