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authorLijian Zhao <lijian.zhao@intel.com>2019-04-22 21:17:58 +0000
committerDuncan Laurie <dlaurie@chromium.org>2019-04-22 21:35:45 +0000
commit7f1a0e6b4c6a319d3cd552c708195d94b99bbb97 (patch)
tree799d6ed0f6794555f094f1d7d8dec6a059fe027a /src/include/sys
parent69eae2762fc34f8303e8a41065df437295262586 (diff)
Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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