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author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-03-08 09:49:15 +0100 |
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committer | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-03-19 09:18:20 +0000 |
commit | d425e881e339e8f92c48237d1e212275c5a7cdc3 (patch) | |
tree | 2a78c4f7b9333c99c968949ea279c601b38a2c24 /src/include/sys | |
parent | f95565311adfd98108a4ece9a2df5de56a3c890d (diff) |
soc/intel/xeon_sp: Add SATC PCI segment group support
For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.
TEST=Booted on ibm/sbp1 with multiple PCI segment groups.
Properly generates multiple SATC headers.
TEST=intel/archercity CRB
Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/include/sys')
0 files changed, 0 insertions, 0 deletions