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authorJeremy Compostella <jeremy.compostella@intel.com>2024-09-25 10:04:36 -0700
committerSubrata Banik <subratabanik@google.com>2024-09-28 18:52:38 +0000
commitbe5745f79f47c5be2c917d63eeb681a58fd8ab2e (patch)
tree55a2b976e2f8401ccec80da6d7e0e80b8f722e1a /src/include/superio
parent7e5765710aca8a322eb76707733b530ad0918353 (diff)
soc/intel/pantherlake: Add FSP-M programming
FSP-M UPDs are programmed according to the configuration (Kconfig and device tree). BUG=348678529 TEST=Memory is initialized successfully and hardware is programmed as desired on Intel pantherlake reference board. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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