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authorJohn Zhao <john.zhao@intel.com>2020-06-24 23:08:01 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-01 05:20:50 +0000
commitc47e3147539a5e91a95a83ba2cd10e9b98039b24 (patch)
tree176db9da227fe1e0aee9d0ee0f8804dba509580f /src/include/superio/hwm5_conf.h
parenta65afdb833741735cf2cdf1386a9a2d065de6065 (diff)
soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4
This change adds Platform-Wide _OSC capabilities for native USB4 support. There is Engineering Change Request (ECR) with _OSC addition for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18 as native USB4 support. The OS sets this bit to indicate support for an OSPM-native USB4 Connection Manager which handles USB4 connection events and link management. The OS use the _OSC mechanism and the bit defined in this ECR to obtain configuration and connection management capabilities of USB4 connections. This change also fixs the byte index for the DWord-addressable field CDW3 from the capabilities buffer. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/42821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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