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authorSubrata Banik <subrata.banik@intel.com>2021-05-05 19:46:09 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-05-12 06:16:05 +0000
commit8d2b0dcc4447e5189bf993f9b4854dfbd08fb55c (patch)
treea7547d6599506e43e52621b880e3e5cc6096d537 /src/include/stddef.h
parent38e4a2d4cf3398d56640b03371ff1bd08b30aff5 (diff)
include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/include/stddef.h')
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