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author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-08-28 13:22:30 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:31:35 +0000 |
commit | dc87025ce41f24c8c3337176c3e38f230e7a0aa9 (patch) | |
tree | 9d69cae7f9f6d00c61bec7bd7d5a95f2dbcccd96 /src/include/stdarg.h | |
parent | 6727276a659968b509b79bf559dc25a71305bc6e (diff) |
soc/intel/tigerlake: Skip GPIO configuration from FSP
FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.
BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2
Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/stdarg.h')
0 files changed, 0 insertions, 0 deletions