spi_flash: Add Dual SPI support

This patch adds support to read SPI flash in Dual SPI mode, where both
MISO and MOSI lines are used for output mode (specifically Fast Read
Dual Output (0x3b) where the command is still sent normally, not Fast
Read Dual I/O (0xbb) whose additional benefit should be extremely
marginal for our use cases but which would be more complicated to
implement). This feature needs to be supported by both the flash chip
and the controller, so we add a new dual_spi flag (and a new flags field
to hold it) to the spi_flash structure and a new optional xfer_dual()
function pointer to the spi_ctrlr structure. When both are provided,
Dual SPI mode is used automatically, otherwise things work as before.

This patch only adds the dual_spi flag exemplary to all Winbond and
Gigadevice chips, other vendors need to be added as needed.

Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 936b0abe85..3a0c383676 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -90,6 +90,13 @@ struct spi_flash_ops {
 struct spi_flash {
 	struct spi_slave spi;
 	u8 vendor;
+	union {
+		u8 raw;
+		struct {
+			u8 dual_spi	: 1;
+			u8 _reserved	: 7;
+		};
+	} flags;
 	u16 model;
 	const char *name;
 	u32 size;