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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-27 13:17:14 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2015-11-29 19:36:34 +0100 |
commit | 0eb163d5d37bd497dcb0a9b8e0c40404617c8af7 (patch) | |
tree | 163a86a86c9498bd5fa28b4dd9d5c39df4e3dc37 /src/include/spi_flash.h | |
parent | 2ca8b31ff54dd69a39e3c222f4512f46010507e3 (diff) |
nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set
Also fix incorrect Trfc[0-3] value on Family 15h.
Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include/spi_flash.h')
0 files changed, 0 insertions, 0 deletions