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| author | V Sowmya <v.sowmya@intel.com> | 2022-05-17 14:14:39 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-20 20:26:58 +0000 |
| commit | fe97ad37fcee9820a796aaa7f88c0cb2c287c348 (patch) | |
| tree | 58973a45316de3d3fac605d5fe8357f5b9301fae /src/include/spi-generic.h | |
| parent | 1e44a5b0c71b959c87340f59e9b7629554824445 (diff) | |
mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for Nereid
This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/include/spi-generic.h')
0 files changed, 0 insertions, 0 deletions