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| author | Shuo Liu <shuo.liu@intel.com> | 2024-04-25 05:41:16 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-04-29 15:40:07 +0000 |
| commit | 78439118c8263160818bc5a2cb68f7a8be0e5a26 (patch) | |
| tree | 503f6e7505862ee2dac454e929249ac1e2719396 /src/include/spi-generic.h | |
| parent | b84d55b582d0cd48078f039b0b5ea4e8896189e5 (diff) | |
soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.
Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/include/spi-generic.h')
0 files changed, 0 insertions, 0 deletions