summaryrefslogtreecommitdiff
path: root/src/include/spi-generic.h
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2017-11-03 16:49:01 -0700
committerAaron Durbin <adurbin@chromium.org>2017-11-07 21:05:27 +0000
commita5b88e442bac16fcce7d9d46dea6cf7c6103d5e1 (patch)
tree1ac2555c3820c87aa33138e60ee78d84efe01356 /src/include/spi-generic.h
parentd038d53a33e4dae29db82b2dcb276ff5ae9d4a14 (diff)
intel/cannonlake_rvp: Clean up GPIO programming
Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4 platform, it is also critical to revisit the GPIO settings as they are different. Remove unused GPIO setting for old platform, and clean up the native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set to GPIO mode is illegal. TEST=Boot up in chromeos successfully. Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/include/spi-generic.h')
0 files changed, 0 insertions, 0 deletions