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authorElyes Haouas <ehaouas@noos.fr>2022-12-28 12:33:58 +0100
committerElyes Haouas <ehaouas@noos.fr>2023-01-04 12:39:32 +0000
commitf82e68c900151efae572e3bc19690e978b82ca1b (patch)
treefb3709fdb6601c2417baac81219d71fe999c433f /src/include/spd.h
parentaf6cd3f0b44a39bb6387c8218e5872afb74fcc3f (diff)
spd.h: Move enum ddr3_module_type to ddr3.h
Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/spd.h')
-rw-r--r--src/include/spd.h17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/include/spd.h b/src/include/spd.h
index 25d04639fc..2fe9f968d4 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -201,23 +201,6 @@ enum spd_memory_type {
#define SPD_ECC_8BIT (1<<3)
#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
-/* Byte 3 [3:0]: DDR3 Module type information */
-enum ddr3_module_type {
- DDR3_SPD_RDIMM = 0x01,
- DDR3_SPD_UDIMM = 0x02,
- DDR3_SPD_SODIMM = 0x03,
- DDR3_SPD_MICRO_DIMM = 0x04,
- DDR3_SPD_MINI_RDIMM = 0x05,
- DDR3_SPD_MINI_UDIMM = 0x06,
- DDR3_SPD_MINI_CDIMM = 0x07,
- DDR3_SPD_72B_SO_UDIMM = 0x08,
- DDR3_SPD_72B_SO_RDIMM = 0x09,
- DDR3_SPD_72B_SO_CDIMM = 0x0a,
- DDR3_SPD_LRDIMM = 0x0b,
- DDR3_SPD_16B_SO_DIMM = 0x0c,
- DDR3_SPD_32B_SO_RDIMM = 0x0d,
-};
-
/* Byte 3 [3:0]: DDR4 Module type information */
enum ddr4_module_type {
DDR4_SPD_RDIMM = 0x01,