diff options
author | Subrata Banik <subrata.banik@intel.com> | 2021-10-26 13:19:20 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 08:13:25 +0000 |
commit | 3306f37fd60ddb19e78816327dc0655dbf39186e (patch) | |
tree | 3da44350f39f599217c0d9276824a666f0df39d0 /src/include/spd.h | |
parent | 35bcf5071ccf3c4a56445b172b64d2ce515a39e9 (diff) |
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
Add DDR5 and LPDDR5 memory type checks while calculating bus width
extension (in bits).
Additionally, update all caller functions of
smbios_bus_width_to_spd_width() to pass `MemoryType` as argument.
Update `test_smbios_bus_width_to_spd_width()` to accommodate
different memory types.
Create new macro to fix incorrect bus width reporting
on platform with DDR5 and LPDDR5 memory.
With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit
primary bus width per Ch showed the Total width as:
Handle 0x000F, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0009
Error Information Handle: Not Provided
Total Width: 80 bits
Data Width: 64 bits
Size: 16 GB
...
BUG=b:194659789
Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`.
Change-Id: I79ec64c9d522a34cb44b3f575725571823048380
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/include/spd.h')
-rw-r--r-- | src/include/spd.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/spd.h b/src/include/spd.h index ec5296ec2f..af3072e8ec 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -209,5 +209,6 @@ enum spd_memory_type { #define SPD_MINI_UDIMM 0x20 #define SPD_ECC_8BIT (1<<3) +#define SPD_ECC_8BIT_LP5_DDR5 (1<<4) #endif |