diff options
author | Keith Short <keithshort@chromium.org> | 2019-05-10 11:14:31 -0600 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-22 17:45:11 +0000 |
commit | c58e3bd90a96bf01859d1c0af83926b1e17edff5 (patch) | |
tree | 15eb21e5c0f6c9402b9d9fb11b4e85907528da24 /src/include/sar.h | |
parent | 15588b03b36aa875e2a2a31cc649a2d9dff7581e (diff) |
post_code: add post code for video initialization failure
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/include/sar.h')
0 files changed, 0 insertions, 0 deletions