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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-21 17:09:08 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-21 17:47:53 +0000
commit732e9e63826f1100953b5c91259e77f4f305d6af (patch)
tree5f5a3d40e034a323883ced665a610c6ee17f3ad4 /src/include/sar.h
parent8b0636e06f0e5e20022baaa57625c7c8d9c1457c (diff)
mb/google/octopus: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by adding an appropriate early gpio table in the bootblock. The soc code gets dropped in CB:49410. Change-Id: Ie33bae481f430a1c4410a0a4e2b2a34a3e78adaa Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49411 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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