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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 09:48:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-02 07:15:53 +0000 |
| commit | 924fe94075b9559d8f6469413cf61589c49538da (patch) | |
| tree | feba907371cbbd2e420b991d1d90b8eb06346ac3 /src/include/post.h | |
| parent | 5d79a0cc5ad7e58b240be3d3531bfa1df225534d (diff) | |
soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/post.h')
0 files changed, 0 insertions, 0 deletions