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authorMartin Roth <martin.roth@amd.com>2023-01-09 21:21:48 -0700
committerMartin L Roth <gaumless@gmail.com>2023-01-17 16:08:18 +0000
commitb486fe95bf455008d5d5c6df7e1c1fc836e9ccd1 (patch)
treec319d32e6a64cf914ad8ac5ebdc80f716fc12a76 /src/include/mipi
parent3f5985972d8893614671c81dfec1e915f09e1d1f (diff)
soc/amd: Use fixed EFS location for Phoenix & Glinda
The AMD SoCs no longer have a variable position for EFS - it's now fixed at 0xff020000 - 128KiB into the 16MiB ROM decode region. It's a little more complex than that because the chip can be larger than 16MiB, and the entire ROM can be decoded if mapped above the 4GiB boundary, but we don't currently support doing that in coreboot, so this is enough for now. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I343a875ba9aa8294a090f2eff7b5dfb5e86334f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/include/mipi')
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