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authorMartin Roth <gaumless@gmail.com>2022-11-03 18:52:51 -0600
committerMartin L Roth <gaumless@gmail.com>2022-11-12 22:53:14 +0000
commit60293e9b1f4cec45c28d7de3aa42e35faebe4b99 (patch)
tree56933cbcf30db1f72b7fa1119f1bc2d3b2f12ebe /src/include/mipi/panel.h
parent9a8667a841f14af61f50a3fba4e0734f24ff24b2 (diff)
lib/ramtest.c: Update ram failure post code
coreboot already has a ram failure post code defined, but the ram test functions weren't using it, and were using 0xea instead. This changes those failures to display 0xe3, the value defined in post_codes.h by POST_RAM_FAILURE. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/include/mipi/panel.h')
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