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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-11 20:58:18 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-14 16:41:57 +0200 |
commit | d22206ac796b747ad1e790e2dc44cdf8832d66e8 (patch) | |
tree | ca3843e7b012f6cbcd21f9bcf3e7632a2d7655eb /src/include/memrange.h | |
parent | 0430c69918ea463d601a40aa3865245e56e8fa9c (diff) |
superio/nct5104d: Handle shared GPIO/UART pins
Routing is decided based on enabled logical/virtual devices.
For a valid devicetree, one should have only one of SP3 and GPIO0,
and only one of SP4 and GPIO1, enabled at a time in configuration.
Change-Id: I02017786aba9dd22d12403aaa71d7641f5bbf997
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Diffstat (limited to 'src/include/memrange.h')
0 files changed, 0 insertions, 0 deletions