diff options
| author | Martin Roth <martinroth@chromium.org> | 2021-03-21 18:45:16 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-04-05 18:24:44 +0000 |
| commit | 632419852af370f8d6d28ba87ecbfc267073333a (patch) | |
| tree | 33f9f6f027dd16829f16af30d33bf50d54cc7c0b /src/include/memrange.h | |
| parent | d07f724f9c3a310168a38cbef7253ec9cf46bde6 (diff) | |
mb/google/guybrush: Update GPIO configuration
Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.
BUG=b:183340503
TEST=Boot Guybrush
Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/memrange.h')
0 files changed, 0 insertions, 0 deletions