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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2024-04-24 11:51:59 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-05-06 11:22:42 +0000
commit653ba223df6b949743080f837760ed9c1264cca7 (patch)
treef71ab5563e99080a2691515ef4f9afd4986e4ad2 /src/include/memory_info.h
parent4fa835421690f233f739e18f6037f8549330e556 (diff)
common/block/tcss: Add config for PDC<->PMC mux configuration
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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