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authorElyes Haouas <ehaouas@noos.fr>2024-05-06 11:48:41 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-05-07 10:53:31 +0000
commit8bcd8210ea64bdbb35485d361e645f2c9cfcf763 (patch)
tree7f36324e0d9e90e03f239974c7ae99220616c6d7 /src/include/device
parent0f45e17f564a657ddf9804124e4e30da0edb1d13 (diff)
dram/ddr3: Use the same naming convention as DDR4
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/dram/ddr3.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 65977b49c1..c4fd253efd 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -27,12 +27,12 @@
*
* @{
*/
-#define SPD_DIMM_MOD_ID1 117
-#define SPD_DIMM_MOD_ID2 118
-#define SPD_DIMM_SERIAL_NUM 122
-#define SPD_DIMM_SERIAL_LEN 4
-#define SPD_DIMM_PART_NUM 128
-#define SPD_DIMM_PART_LEN 18
+#define SPD_DDR3_MOD_ID1 117
+#define SPD_DDR3_MOD_ID2 118
+#define SPD_DDR3_SERIAL_NUM 122
+#define SPD_DDR3_SERIAL_LEN 4
+#define SPD_DDR3_PART_NUM 128
+#define SPD_DDR3_PART_LEN 18
/** @} */
/* Byte 3 [3:0]: DDR3 Module type information */
@@ -145,7 +145,7 @@ struct dimm_attr_ddr3_st {
/* ASCII part number - NULL terminated */
u8 part_number[17];
/* Serial number */
- u8 serial[SPD_DIMM_SERIAL_LEN];
+ u8 serial[SPD_DDR3_SERIAL_LEN];
};
enum ddr3_xmp_profile {