diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-06-13 20:42:44 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-22 17:31:42 +0000 |
| commit | 88f863cfbb1f3f547cf503b462e29c285e8f1c94 (patch) | |
| tree | 6df7c2e9cd197cdec96c88b31c39a6495ebc5764 /src/include/device | |
| parent | f00c0a8f4ac0928da36b752bb66a825e7b1ed014 (diff) | |
soc/intel: Add Meteor Lake SA device ID
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W).
BUG=b:224325352
TEST=Able to build MTL SoC and verified SA DID is now shown proper.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fc36cbce37..c997da44b4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4133,6 +4133,7 @@ #define PCI_DID_INTEL_MTL_M_ID 0x7D00 #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 +#define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 |