diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-11-27 14:11:02 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-11-29 03:20:54 +0000 |
| commit | 75a7c6e7a9ad9d64a665750653a7307ea556a2d0 (patch) | |
| tree | 55301867dcb7147cc7143e377ed930cfe3396f6e /src/include/device | |
| parent | 777ffff4421a9ab0961f2284e7448307f3c5154f (diff) | |
pci_mmio_cfg: Rename pcicfg to pci_map_bus
Rename pcicfg to pci_map_bus and add prototype for the platforms not
supporting ECAM.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_mmio_cfg.h | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index cabf5b79ee..89c99062d2 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -40,11 +40,17 @@ union pci_bank { extern u8 *const pci_mmconf; static __always_inline -volatile union pci_bank *pcicfg(pci_devfn_t dev) +volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)]; } +#else + +/* For platforms not supporting ECAM, they need to define pci_map_bus function + * in their platform-specific code */ +volatile union pci_bank *pci_map_bus(pci_devfn_t dev); + #endif /* @@ -56,37 +62,37 @@ volatile union pci_bank *pcicfg(pci_devfn_t dev) static __always_inline uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg8[reg]; + return pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } static __always_inline void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { - pcicfg(dev)->reg8[reg] = value; + pci_map_bus(dev)->reg8[reg] = value; } static __always_inline void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { - pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value; + pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)] = value; } static __always_inline void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { - pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; + pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)] = value; } /* @@ -98,19 +104,19 @@ void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) static __always_inline uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) { - return (uint8_t *)&pcicfg(dev)->reg8[reg]; + return (uint8_t *)&pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg) { - return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return (uint16_t *)&pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg) { - return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return (uint32_t *)&pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } #endif /* _PCI_MMIO_CFG_H */ |