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| author | Usha P <usha.p@intel.com> | 2021-11-15 18:40:00 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-29 09:46:40 +0000 |
| commit | 5b94cd9e9d0aae0bfba68fa65bf94a0d5985fa87 (patch) | |
| tree | f5f320155db2cb55c5ffad610ab693de9d5fe790 /src/include/device | |
| parent | 248dbe0908f1b934d465550987a2497cd6593b4b (diff) | |
soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 63b735f7d7..db51905598 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3886,6 +3886,10 @@ #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa #define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT1 0x46D0 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT2 0x46D1 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT3 0x46D2 + /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3997,6 +4001,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f #define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B + /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 |