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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-05-16 14:56:22 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-07-19 13:52:28 +0000
commit4e2f95b789d8f3b505f52c42b634401dd5f718a2 (patch)
tree930ee662200f158b5c442c4481df76b276c99a97 /src/include/device
parentfe98e90671b1ff06e924ae09062814050bdb3996 (diff)
device/pci: Add MSI-X helper functions
Basic PCI MSI-X table helper functions. Imported from GNU/Linux kernel PCI subsystem. To be used on Cavium to configure MSI-X tables. Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26329 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci.h18
-rw-r--r--src/include/device/pci_def.h12
2 files changed, 30 insertions, 0 deletions
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 3cc2c64e4f..f1ab91bbc7 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -56,6 +56,20 @@ struct pci_driver {
const unsigned short *devices;
};
+struct msix_entry {
+ union {
+ struct {
+ u32 lower_addr;
+ u32 upper_addr;
+ };
+ struct {
+ u64 addr;
+ };
+ };
+ u32 data;
+ u32 vec_control;
+};
+
#ifdef __SIMPLE_DEVICE__
#define __pci_driver __attribute__((unused))
#else
@@ -104,6 +118,10 @@ void pci_assign_irqs(unsigned int bus, unsigned int slot,
const char *get_pci_class_name(struct device *dev);
const char *get_pci_subclass_name(struct device *dev);
+size_t pci_msix_table_size(struct device *dev);
+int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx);
+struct msix_entry *pci_msix_get_table(struct device *dev);
+
#define PCI_IO_BRIDGE_ALIGN 4096
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 60d913204a..f9ce1a6382 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -292,6 +292,18 @@
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
+/* MSI-X registers */
+#define PCI_MSIX_FLAGS 2
+#define PCI_MSIX_FLAGS_QSIZE 0x7FF /* table size */
+#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
+#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
+#define PCI_MSIX_TABLE 4 /* Table offset */
+#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
+#define PCI_MSIX_PBA_BIR 0x7 /* BAR index */
+#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
+#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
+
+
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */