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authorSaurabh Mishra <mishra.saurabh@intel.com>2024-04-12 20:49:48 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-05-14 13:10:34 +0000
commit47e7240ffc6a8f479bedc065376fb59cd040c7c7 (patch)
treebdc5f0af9f053f5ed10ed2add315a3bf58e84375 /src/include/device
parente3b1a9d7a1074e1ce066a1f11775fdd953b9a98f (diff)
soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDs
Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 5500d279bf..e349d2790d 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4599,6 +4599,7 @@
#define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e
#define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f
#define PCI_DID_INTEL_LNL_TBT_RP2 0xa860
+#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837
#define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833
#define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834
@@ -4706,6 +4707,9 @@
#define PCI_DID_INTEL_LNL_PSE1 0xa863
#define PCI_DID_INTEL_LNL_PSE2 0xa864
+/* In-memory Analytics Accelerator device IDs */
+#define PCI_DID_INTEL_LNL_IAA 0x642d
+
/* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d
#define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d