diff options
| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-12-08 11:05:36 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-24 12:48:18 +0000 |
| commit | 2ccbcc560f01a7cd646b5012c3f680623c43ef96 (patch) | |
| tree | 0e160a153bb1cc1e6f88ddbaee891d47b9e68857 /src/include/device | |
| parent | 1364ac3478c69affce32840d92577f5a8da2eb8c (diff) | |
soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SP
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched
on Jan. 10, 2023. The chipset includes Emmitsburg PCH.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 15a41ce072..dbc17062fe 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4120,6 +4120,7 @@ #define PCI_DID_INTEL_GLK_SMBUS 0x31d4 #define PCI_DID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DID_INTEL_SPT_H_SMBUS 0xa123 +#define PCI_DID_INTEL_EBG_SMBUS 0x1bc9 #define PCI_DID_INTEL_LWB_SMBUS 0xa1a3 #define PCI_DID_INTEL_LWB_SMBUS_SUPER 0xa223 #define PCI_DID_INTEL_CNL_SMBUS 0x9da3 @@ -4192,6 +4193,7 @@ #define PCI_DID_INTEL_ADP_P_P2SB 0x7a20 #define PCI_DID_INTEL_ADP_S_P2SB 0x7aa0 #define PCI_DID_INTEL_ADP_M_P2SB 0x54a0 +#define PCI_DID_INTEL_SPR_SP_P2SB 0x1bc6 #define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20 #define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 |