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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2020-04-22 12:13:40 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-04-28 09:39:42 +0000
commit8745a2743c046352725957c1657514b0d49309a6 (patch)
tree765ac046da3797bc7bccc7faaa3221bd87a8b780 /src/include/device
parent8536072346efa0919f82c7355a1cf03147dda8b9 (diff)
soc/intel/jasperlake: Add new MCH device ids
Add new MCH device-ids for jasperlake. Reference is taken from jasperlake EDS volume 1 chapter 13.3. BUG=None BRANCH=None TEST=code compiles and able to boot the platform. Change-Id: I38e09579c9a3681e9168c66085cbb3a092dc30cc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 3de67ca7dd..2ef3aa37d3 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3508,6 +3508,9 @@
#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532
#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22
+#define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26
+#define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12
+#define PCI_DEVICE_ID_INTEL_JSL_ID_4 0x4e14
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23