diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2021-03-06 10:31:46 -0800 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-03-11 04:26:21 +0000 |
| commit | 492a792d3872ee2683db169fb011daf87b71bff9 (patch) | |
| tree | 6c37d7173aa9b6d08865be738113ce92023460a8 /src/include/device | |
| parent | 238242bda42a42b4f8608d73a27d5e3a6bc54a13 (diff) | |
soc/intel/common/block: Add PCI IDs for EmmitsBurg PCH
According to Intel EmmitsBurg EDS, doc# 606161:
* Add PCI devid for SPI.
* Add PCI devid for ESPI (LPC).
EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids
Scalable Processor (SPR-SP).
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b54de0bdb2..a3382df4ef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3037,6 +3037,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f +#define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3675,6 +3676,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_SPI1 0x54ab #define PCI_DEVICE_ID_INTEL_ADP_M_SPI2 0x54fb +#define PCI_DEVICE_ID_INTEL_SPR_HWSEQ_SPI 0x1bca + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 |