diff options
| author | Selma Bensaid <selma.bensaid@intel.com> | 2021-09-23 18:45:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-29 10:07:41 +0000 |
| commit | 326a2c4794e392df2803a22cbaca66dbb5ed58fd (patch) | |
| tree | f99bdfbd6a0672c4f2730ef132dce3920aeff43c /src/include/device | |
| parent | 3e97178871869c8f05cbed2a7d18d8e3928f898b (diff) | |
soc/intel/alderlake: Add GFx Device ID 0x46c3
This CL adds support for new ADL-M graphics Device ID 0x46c3.
TEST=boot to OS
Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c36c1c6b42..be4ce76087 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3880,6 +3880,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa +#define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 |