diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-29 15:20:56 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-07-07 20:31:14 +0000 |
| commit | c5316ec4d675750f35ff1b383adacc2255e92d79 (patch) | |
| tree | 9def7221ee37b1c5939f7a9d35e8ba5f0c0fd942 /src/include/device | |
| parent | 3452cb1359229b0457e9e1f6282c67fd459d4c90 (diff) | |
soc/intel/common/block: Add new block DTT
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.
Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ed0629a7fb..8d16361405 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3717,6 +3717,9 @@ #define PCI_DEVICE_ID_INTEL_TGL_IPU 0x9a19 #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 +/* Intel Dynamic Tuning Technology Device */ +#define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 + #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 #define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 |